1. Field of the Invention
The embodiments herein generally relate to field effect transistors (FETs) and, more particularly, to an asymmetric FET structure and method of forming the structure that provides minimal resistance in the source region and minimal capacitance between gate and drain region in order to optimize performance.
2. Description of the Related Art
In conventional symmetric planar metal oxide semiconductor field effect transistors (MOSFETs), there is an intrinsic trade-off between source/drain series resistance and gate to source/drain capacitance. Specifically, FET saturated currents are more sensitive to source resistance and less sensitive to drain resistance. That is, FET drive current improves more with reduced source resistance, than with reduced drain resistance. Additionally, circuit delay is more sensitive to gate to drain capacitance than gate to source capacitance. That is, due to the Miller effect, the gate to drain capacitance can impact circuit delay significantly more than gate to source capacitance. However, techniques associated with reducing source/drain resistance to improve drive current often simultaneously increase the gate to drain capacitance, thereby increasing circuit delay. Similarly, techniques associated with reducing gate to source/drain capacitance often simultaneously increase source resistance, thereby degrading drive current. Thus, there is often an intrinsic trade-off between decreasing source resistance to improve drive current and decreasing gate to drain capacitance to minimize circuit delay.